in this video we discuss using JK

flip-flops to build a Ripple counter and using D flip-flops to build a BCD, binary

coded decimal counter. We first discuss the Ripple counter. As shown in this diagram, we tie the JK’s of all flip flops to high. That means the input values of JK are 11.

So the flip-flop toggles when there is a positive clock transition. In the circuit, the first flip-flop is

driven by a clock but the second flip flop, its clock is connected to Q0 bar of

the first flip-flop, so when there is a transition of Q0 bar from 0 to 1 then Q1

changes state and in the third flip flop, the clock is connected to Q1 bar.

So when Q1 bar changes from 0 to 1, then Q2 toggles. Note that when Q1 bar

changes from 0 to 1, Q1 actually changes from 1 to 0. So the timing diagram here shows the details. At first, all the flip flops have values 0 and when there’s a clock transition, positive transition, it triggers Q0 to toggle from 0 to 1 but there’s no

change in Q1 value because when Q0 changes from 0 to 1, Q0 bar changes from

1 to 0 and there’s no change, no state change when there’s a negative clock

transition. On the other hand, in the second positive

clock transition, Q0 toggles again, so it changes from 1 to 0. That means Q0 bar

changes from 0 to 1, so it toggles Q1 to change it from 0 to 1. Similarly when Q1

changes from 1 to 0 or Q1 bar changes from 0 to 1 then it triggers Q2 to

toggle from 0 to 1. So we have this timing diagram. As you can see, at the

beginning we have Q2 Q1 Q0 as 000 and then 001 representing the value 1,

then 010 representing 2 and then 011, 100, 101 and so on. So you can see

that these actually is a counter counting from 0 1 2 3 4 5 6 7 and back to 0. Now let’s discuss how we implement this

circuit using Verilog program. Okay, I have written the program. So this is the implementation of D

flip-flop with reset as we discussed before and we use positive edge and this

is the implementation of JK flip-flop. So we have the input clock and input

reset an input J, input K and output register Q and output wire Qb, which is the

complement of Q, or Q-bar. We use wire here so that the value [can be] obtained from Q by using assign like this. Qb is basically the complement of Q and the implementation is straightforward.

We have [email protected], positive edge ck, and positive edge rst. if ( rst )

and we have Q assigned 0, otherwise, depending on JK, if

JK equals 00, then there’s no change, so the next state of Q is

equal to the current state and if JK equals to 01, we have reset. That

means the next state of Q is 0. If it is 10 then we have set. That means the

next state of Q is 1 and ifJK equals 11, then we toggle. That means

Q next state is equal to the complement of the current state: Q

assigned negation Q. So this is JK and we use JK flip-flops to construct a

4-bit ripple counter, a binary counter. So we have input ck and input rst,

the reset and output 3 to 0, 4-bit Q and also Qb, the complement of Q. So we just

create 4 JK flip-flops, the first is a, ck, rst; the JK values are 11 and

the Q0, Q0 bar; the second, Qb0 as you can see from this diagram the clock

is Q0 bar. so that’s what we have. Qb0 is Q0 bar.

And again, the rst; JK values are 11 and output Q1, Qb1

and this Qb1 is the input to the clock of the next flip flip c and again we have

rst as input; the JK values are 11 and the outputs are Q2 and Qb2 and

this Qb2 will be the input to the clock of the next stage. This is the clock

of flip flop d and again the other input is rst; JK values are 11 and the outputs are

Q3, Qb3 and you can easily write a test bench to

test this. This is the test bench, so we have inputs reg ck, and

reg rst and outputs wire Q, 4 bits, Qb, 4 bits. So we just create

an instance of the RippleCounter: ck goes ck, rst goes to rst, Q

goes to Q, Qb goes to Qb and then we display the clock, the time and Q. So we

start with ck, the clock to be 1 and reset to be 1 so that all the Q values are 0

and then we set rst to be 0 so the clock will start to function

and we run this for 260 units, and for every ten units we toggle the

clock. So we can compile this. Suppose I compile this. So no error! So we run this. You can

see that we have these outputs. The time at the beginning, we set this [rst] 1 so

everything is 0000 and then the clock changes from 1 to 0. This is negative

transition so there’s no change with the value and here with the transition from

0 to 1 then Q0 toggles so we have 0001 and when the clock changes from 1 to 0

there’s no change in the value and when it changes from 0 to 1, Q0 changes from

from 1 to 0 and Q 1 changes from 0 to 1 and then next we have 0011 ,0100 and 0101 and so on Now we can also see the timing diagrams by

running this code using ISE. Suppose we make a directory, calling it ise. and we run the ise. So ise starts. Click OK for the tips, and we can first close

any current projects and we create a new project. We create the directory we just created. Suppose we call the project name counter and next next finish and we can add copy-of-source to this

project. The source code we’ve just written .. not we this one .. and we also need to add the other source

the test bench and then we have to click simulation. This is the code we just discussed. I think we copied the wrong one. it should be

this: the test bench. Okay this is the one we want. We just

discussed and we click here and we can

double click here to check the syntax so there’s no error. We double click

here to run it, and we can click here to see the timing

diagram. Click here! Now you can see that this is the clock; this is the reset. When this is 0

the clock plays the normal role and you can see that this is the Q; this is Q bar.

So we have a Q0, Q1, Q2, Q3. This is the complement of the

corresponding bits. So at the beginning, it is 0000 and then 0010, 0011 and you can see that it changes state when there is a positive

clock transition like here. When the clock changes from 0 to 1, it changes from 0000

to 0001 and here it changes, the bit changes from 1 to 0

and this changes 0 to 1 and so on. So this is the timing diagram for the

RippleCounter. And next,

we will discuss the BCD counter. Now this is a block diagram showing a

4-bit BCD counter with reset. So basically we will use 4 D flip-flops and

this is the reset and all the D flip-flops are driven by the same clock. So

we have four bits output and call them Q0, Q1, Q2, Q3 and

this is the state diagram. So we start from zero zero zero then the next

state is zero zero one, the next is 010 and so on. It counts all the way up to

nine represented by 1001 then it goes back to 0 and so on so this is

binary coded decimal counter because it only comes up to nine represented

by 1001. So we’ll use 4 D flip flops to implemented this and

this is the state table. This is the present state represented by Q0 Q1 Q2

Q3 and the next state is Q( t +1). We discussed before that Q (t + 1) is

equal to D(t) meaning they can be represented by D 3 D 2 D 1 D 0. So if the

current state is 0000, the next state is 00001 as shown in this state diagram

and if the present state is 0001, the next state is 0010 and so on. We have all the way up to 1001 and the

next state will be zero again and for other values of Q, we don’t care

so they are represented by X. Now

to construct this circuit we have to find out the relation between the D’s

and the Q’s so each of this D is a function of Q3 Q2 Q1 Q0. For example,

for D2 we have to look at this column, okay.

D2 equals zero when Q3 Q2 Q1 Q0 are 0 0 0 0 and it is 0 when it is 0 0 0 1 so

these values can be represented by a k-map as shown here. So we use gray code here, so here we have 0 0 0 1 so we have 0 0 0 1 and then 1 1 1 0 to the 1 1 1 0.

Remember this is a gray code and then 0 0, 00

others are don’t cares and we can find the equation for D2 by

grouping the ones together. For these two ones we form this bubble so we

have from here to here Q3 changes so we get rid of Q3 so we have Q2

only and from here to here Q0 changes so we get rid of Q0; we have Q1bar so we

have this term Q2 Q1-bar, and then for this bubble to we have Q2 and Q0-bar and then for the other term, for

this guy we have Q2-bar and Q1 Q0. Okay so we have

these three terms and we can simplify this a little bit. For these two terms we

can take the Q2 out and for this we can group the Q1 Q0 together so we have

this Q 2 and Q1 bar or Q0 bar and then we apply the De Morgan’s Rule to this term so

we get Q1 and Q0 bar. This is still Q2 and this is Q2 bar and Q1 Q0 so we

can see that if we consider this as a term say A, so we have Q2 A bar or Q2-bar A. So basically, this is an exclusive or. So we have Q2 exclusive or

Q1 Q0. That’s what we obtained this D2 equation. Similarly. we obtained the equation for D3 and D1 and D0. These are the actual equations. So

actually, D0 equals Q0 bar D1 …….. ……. and now the implementation of this using

Verilog is straightforward. I have written the code. So this is the BCD counter. We

have the input ck, the clock, input rst or reset and 3 bits output, sorry 4

bits output Q and we just follow these boolean equations. We define four bits D. So we assign D0 to be a complement

of Q0 and D1 to be the complement of Q3 and Q1 exclusive or Q0 and so on and we

create four flip-flops. These are synchronously clocked. So all the flip flops are driven by the same clock, same reset and each of them has its own D, D0,D1,D2, D3 and its own output Q0 Q1 Q2 Q3 and the relation between D and Q is given by this equation which is what we got and we can easily write a test bench, which is shown here. It’s similar to what we had.

Again, the inputs, the clock, the rst and output, 4 bits Q and we

instantiate the unit under test, ck goes to ck, rst goes to rst, Q

goes to Q and the output 4 bits of Q and the clock and again at the

beginning the clock is 1 and rst is 1 then we set rest to be 0 and the chips will

work as normal and we run that for 260 units. We toggle the clock

every 10 units, 10 times units. Now when we run this, we have something this. So let’s first compile it. We can see the output here again it toggles when

there’s a clock transition from 0 to 1; it counts as 0000 and then 0001, 0010.

Now when it goes from 1 to 0 there’s no change in state; there’s a change in

state when there’s a positive transition from 0 to 1 so you can see that it counts as a BCD counter ….. ..

and then after that it goes back to 0000, 0001. So it works as expected

and again we can run using ise. This is the test bench. and with double click here to check. No error! And then double click here

to run Oh let me try this. I think I need to update this DFF. Now you can see the timing diagram here

again you can see that this is the clock this is reset. It counts at the beginning 0000 and when there’s

a clock transition it becomes 0001 and the next zero zero one zero all the way to 1 0 0 1 and then goes

back to 0 0 0 0 okay so that’s the BCD counter

and here’s the text output so again try this yourself

thank you bye-bye. Oh, maybe I move this;, maybe it was out of the screen so you

can see that it counts from 0000 all the way to one zero zero one, get back to zero zero

zero zero. Thank you bye-bye.